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dec. 2008 2-output high-efficiency step-down switching regulators with built-in power mosfet single-chip type with built-in fet switching regulator series description technical note bd9302fp the bd9302fp is a 2-channel step-down switching regulator controller with a 2.5-mhz, 2-a power switch and available for 2.5-mhz high speed switching operation, which facilitates settings of switching frequency with external resistance, supporting for a wide input voltage range of 6 to 18 v. furthermore, due to a low reference voltage of 0.6 v, this bd9302fp is an l/c best suited to high-voltage input/low-voltage output applications, for example, to step down a voltage from 12 v to 1.2 v. features 1) a wide input voltage range of 6 v to 18 v 2) easy switching frequency setting in the range of 200 k to 2.5 mhz. 3) two built-in power switches of 0.4 , 2 a. 4) 180? phase shift 5) built-in under voltage lock out circuit 6) built-in overcurrent protection circuit 7) built-in thermal shutdown circuit use power supply for dps requiring two power sources adsl modem/plasma display audio devices
2/16 absolute maximum ratings (ta=25 ?c) electrical characteristics * should be derated by 11.6 mw/ ?c at ta=25?c or more. when mounted on a glass epoxy pcb of 70 701.6 mm) ** should not exceed pd-value. [triangular wave oscillator block] oscillation frequency frequency variation [overcurrent protection circuit block] overcurrent limit [under-voltage malfunction prevention circuit block] upper limit threshold voltage lower limit threshold voltage [soft start circuit block] source current sink current clamp voltage shutdown voltage f osc f dvo isw vth vtl isso i ssi vcl v sdwn 1800 ? 2 3.0 2.7 6 0.6 1.75 ? 2000 1 4 3.3 3.0 10 1.7 1.95 ? 2200 ? 6 3.6 3.3 14 5 2.15 0.3 khz % a v v ua ma v v rt=10k ~ 18v vss=1v vss=1v, vcc=3v vcc=3v not designed for radiation resistance. electrical characteristics (unless otherwise specified, ta=25 ? c, vcc=12 v, r t =10 k) typ max item symbol limits min unit conditions power supply voltage power dissipation operating temperature storage temperature output current maximum junction temperature vcc pd topr tstg io tjmax 20 1450* - 40 ~ +85 - 55 ~ +150 2** 150 item symbol rating unit recommended operating range (ta=25 ?c) power supply voltage output current timing resistance oscillation frequency 6 ? 10 100 12 ? ? ? v a k khz item min vcc io rt fosc symbol typ limits unit 18 1.8 100 2500 max * design guarantee (no 100% pre-shipment inspections are conducted.) * v mw ?c ?c ?c a
3/16 electrical characteristics measurement circuit diagram [error amplifier block] input bias current voltage gain comp maximum output voltage comp minimum output voltage output sink current output source current feedback voltage [output block] upper-side on resistance low-side on resistance off current [total device] average supply current i ib av v oh v ol i oi i oo v fb ronh ronl i off i cc ? ? 1.75 ? 1 ? 8 0.588 ? ? 0.1 ? 0.4 200 1.95 0.8 2 ? 4 0.600 0.4 2 0.2 5 1 ? ? 1.0 4 ? 1 0.612 0.6 3 0.4 ? ua v/v v v ma ma v ma ma i comp = - 0.1ma i comp =0.1ma v fb =0.8v v fb =0.4v buffer io=1a* io=20ma* sw=0v r t =1.0v electrical characteristics (unless otherwise specified, ta=25 ? c, vcc=12 v, r t =10 k) typ max item symbol limits min unit conditions fig. 1 typical measurement circuit ? + a v a v v a a v a a v a v ? + a a null amp 10k 1000pf 1000pf 100k 1k 0.6v 10pf 30k 30k 10k 1v 1v 12v 10pf 30k 30k 100k 1k 0.6v null amp 10k 1000pf 1000pf 1uf 5v 1uf 5v 1v pgnd1 comp1 fb1 rt nc ss1 vcc ss2 nc fb2 comp2 gnd pgnd2 sw1l sw1 sw1 boot1 pvcc pvcc pvcc pvcc boot2 sw2 sw2 sw2l v v not designed for radiation resistance. * design guarantee (no 100% pre-shipment inspections are conducted.)
4/16 reference characteristics data (*) the data shown above represent real values sampled but not guarantee values. fig.2 feedback voltage ? ambient temperature 0.50 0.51 0.52 0.53 0.54 0.55 0.56 0.57 0.58 0.59 0.60 0.61 0.62 0.63 0.64 0.65 0.66 feed back voltage : vfb [v] - 40 - 30 - 20 - 10 0 10 20 30405060708085 fig.3 switching frequency ? ambient temperature 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 - 40 - 30 - 20 - 10 0 10 20 30 40 50 60 70 80 85 switching frequency : fsw [khz] ambient temperature : ta [ ?c] ambient temperature : ta [ ?c] ambient temperature : ta [ ?c] fig.4 power supply voltage ? circuit current 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 circuit current : icc [ma] 0123456789 10 11 12 13 14 15 16 17 18 input voltage : vcc [v] - 40?c 25?c 85?c fig.5 sw on resistance ? ambient temperature 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 - 40 - 30 - 20 - 10 0 102030405060708085 ambient temperature : ta [ ?c] - 40 - 30 - 20 - 10 0 102030405060708085 sw on resistance : ronh [ ] fig.6 swl on resistance ? ambient temperature 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 swl on resistance : ronl [ ] fig.7 setting resistance ? switching frequency 10 100 1000 10000 100000 switching frequency : fsw [khz] 10 100 timing resistance : rt [k ] fig.8 switching frequency ? max duty 0 10 20 30 40 50 60 70 80 90 100 max duty [%] 1000 200 2000 switching frequency : fsw [khz] fig.9 switching frequency ? power supply voltage 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 6 7 8 9 10 11 12 13 14 15 16 17 18 input voltage : vcc [v] switching frequency : fsw [khz] efficiency : h [%] fig.10 output current ? efficiency 0 10 20 30 40 50 60 70 80 90 100 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 output current : io [a]
5/16 reference characteristics data application measurement circuit diagram (*) the data shown above represent real values sampled but not guarantee values. 0 10 20 30 40 50 60 70 80 90 100 6 7 8 9 10 11 12 13 14 15 16 17 18 efficiency : h [%] efficiency : h [%] input voltage : vcc [v] fig.13 set capacitance ? delay time ss capacitor : css [ f] delay time : tv01 [ms] fig.11 power supply voltage ? efficiency 0 10 20 30 40 50 60 70 80 90 100 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 switching frequency : fsw [khz] fig.12 switching frequency ? efficiency 0 1 10 100 input voltage output voltage output current output voltage (ac) output current output voltage (ac) fig.16 load transient response no. 2 fig.14 startup waveform fig.15 load transient response no. 1 fig.17 application measurement circuit diagram 0.01 0.10 1.00 1.47ms 12v 2.5v vcc 12v bd9302fp vo1=3.3v 10f 10f 10f 0.1 f 0.1 f 0.1 f 20k 30k 51k 20k 33 pf 33pf 3300 pf 3300pf 30 k 22 k 100 k 0.1 f 10h 10h vo2=1.2v
6/16 pin assignment block diagram pin assignment / functions ground error amplifier output error amplifier inverting input frequency setting resistor connection n.c. soft start capacitor connection (shutdown at low) power supply input soft start capacitor connection (shutdown at low) n.c. error amplifier inverting input error amplifier output ground pgnd1 comp1 fb1 rt ? ss1/sdwn vcc ss2/sdwn ? fb2 comp2 gnd 1 2 3 4 5 6 7 8 9 10 11 12 pin name pin no. function ground switching output 2 (low side) switching output 2 switching output 2 boot capacitor connection power supply input power supply input power supply input power supply input boot capacitor connection switching output 1 switching output 1 switching output 1 (low side) pgnd2 sw2l sw2 sw2 boot2 pvcc pvcc pvcc pvcc boot1 sw1 sw1 sw1l 13 14 15 16 17 18 19 20 21 22 23 24 25 pin name pin no. function fig.18 pin assignment / block diagram comp1 fb1 rt ss1/sdwn vcc n.c. fb2 comp2 gnd ss2/sdwn pgnd1 n.c. pgnd2 17 16 8 9 10 11 12 3 4 6 7 2 ocp 24 23 22 20 19 18 21 sw1 sw1 boot1 pvcc pvcc pvcc pvcc boot2 sw2 sw2 + + - vref - + - current sense current sense sdwn sdwn drv1 set reset uvlo tsd - + 15 err pwm osc 5v pwm err 0.6v 0.6v internal bias slope slope 1 25 5 13 14 sw2l top view sdwn sdwn drv1 set reset drv2 drv2 sw1l ocp sw1l sw1 sw1 boot1 pvcc pvcc fin pvcc pvcc boot2 sw2 sw2 sw2l 25 24 23 22 21 20 19 18 17 16 15 14 1 2 3 4 5 6 7 8 9 10 11 12 13 pgnd1 comp1 fb1 rt n.c. ss1/sdwn fin vcc ss2/sdwn n.c. fb2 comp2 gnd pgnd2
7/16 error amplifier (err) block the err block is a circuit used to compare between the 0.6-v reference voltage and the feedback voltage of output voltage. the comp voltage, a result of this comparison, determines the switching duty. furthermore, soft start function is activated with the ss voltage while in startup operation. consequently, the comp voltage is limited to the ss voltage. oscillator (osc) block the osc block is a block to determine the switching frequency through the rt pin, which is settable in the range of 100 khz to 2500 khz. slope block the slope block is a block to generate a triangular wave from the clock generated with the osc and then to transmit the triangular wave to the pwm comparator. pwm block the pwm block is used to make comparison between the output comp voltage of the error amplifier block and the triangular wave of the slope block, thus determining the switching duty. the switching duty is limited with the maximum duty ratio, which is internally determined, and will not reach 100%. reference voltage (uref) block the uref block is a block to generate a 2.9-v internal reference voltage. protection circuit (uvlo/tsd) block the uvlo (under voltage lock out) circuit is used to shut down the circuit when the voltage falls below approximately 3.3 v, while the tsd (thermal shutdown) circuit is used to shut down the circuit at a temperature of 175 ?c and reset it at a temperature of 160 ?c. overcurrent protection circuit (ocp) this function is used to detect a current passing through the power transistor fet with the current sense and activate the overcurrent protection when the current reaches approximately 4 a. if the overcurrent protection is activated, switching will be turned off to discharge the ss pin capacitance. fig.19 typical application circuit 17 16 8 9 10 11 12 3 4 6 7 2 ocp 24 23 22 20 19 18 21 comp1 fb1 rt ss1/sdwn vcc vcc n.c. 30 k 20 k 3300 pf 33 pf 30 k 22k 20k 51k 3300 pf 0.1 f 0.1 f 33pf 100k fb2 comp2 gnd sw1 sw1 boot1 pvcc pvcc pvcc pvcc boot2 sw2 sw2 + + - vref - + - current sense current sense sdwn sdwn drv1 set reset uvlo tsd - + 15 err pwm osc 5v pwm err 0.6v 0.6v internal bias slope slope ss2/sdwn 1 pgnd1 25 5 n.c. 13 pgnd2 14 sw2l sdwn sdwn drv1 set reset drv2 drv2 sw1l ocp vcc vo : 1.2v 10 f 10 f 0.1 f 10 h vo : 3.3v 10f 0.1f 10 h
8/16 timing chart startup sequence vcc ss sw v out sw vo io vd c normal operation fig.20 startup sequence fig.21 while in normal operation
9/16 external component setting procedure (1) setting of output l constant the coil l used for output is determined according to the rated current i lr and the maximum load current value i omax of the coil. adjust so that (i omax + di l ) will not conflict with the rating. at this time, di l can be obtained according to the formula shown below. furthermore, since the coil l value may also vary by approximately 30%, set this value with an adequate margin. if the coil current i l exceeds the rated coil current i lr , the internal ic element may be damaged. it is recommended to make setting of coil value in the range of 4.7 f to 100 f. (2) setting of output co constant for output capacitor, select the allowable ripple voltage v pp or the allowable drop voltage at a sharp change of load, whichever larger for the capacitor. the output ripple voltage can be obtained according to the formula shown below. design the component so that this constant will fall within the allowable ripple voltage. furthermore, estimate the drop voltage v dr at a sharp change of load according to the formula shown below. however, 10 sec will be the estimated value of the dc/dc converter response speed. make setting of capacitance with thorough consideration given to the margin so that these two values will fall into the specified values. it is recommended to make setting of the capacitance in the range of 10 f to 100 f. if a short circuit occurs, an inverse current passes through the parasitic diode to cause damage to the internal circuits. to prevent that, insert a backflow prevention diode. step-down di l = [a] . . . (1.1) (v cc ? v o ) v o v cc 1 f 1 l ,where f: switching frequency ,where f: switching frequency step-down dv pp = di l [v] r esr + v o v cc di l 2c o 1 f v dr = [v] 10 sec di c o i lr average i omax current adjust so that (iomax + di l ) will not conflict with the rating. t i l fig.22 fig.23 l c o i l v o v cc
10/16 (3) setting of feedback resistance constant in order to make settings of feedback resistance, refer to the formula shown. it is recommended to make setting of resistance in the range of 10 k to 330 k. setting the resistance to 10 k or less will result in degraded power efficiency, while setting it to 330 k or more will increase the offset voltage due to the input bias current of 0.4 a (typ) of the internal error amplifier. (4) setting of oscillation frequency connecting a resistor to the rt pin (pin 4) will allow for the setting of triangular wave oscillation frequency. the rt determines the charge/discharge current to the internal capacitor, with which the frequency varies. referring to figure shown below, make settings of the rt resistor. recommended setting range is 10 to 100 k . be noted that any setting outside of this range may turn off switching, thus impairing the operation guarantee. (5) setting of soft start time the soft start function will be required to prevent an excessive increase in the coil current and overshoot of the output voltage, while in startup operation. figure below shows the relationship between the capacitor and the soft start time. referring to this figure, make the capacitor setting. it is recommended to make setting of capacitance value in the range of 0.01 to 10 f. setting the capacitance value to 0.01 f or less may cause overshoot to the output voltage. if any startup-related function (sequence) of other power supply is provided, use a high-accuracy product (e.g. 5r) or the like. furthermore, since the soft start time varies with the input voltage, output voltage, load, coil, output capacitor, or else, be sure to check to be sure this soft start time on the actual system. 10 100 1000 10000 100000 switching frequency : fsw [khz] 10 100 timing resistance : rt [k ] ss capacitor : css [ f] delay time : tv01 [ms] 0 1 10 100 0.01 0.10 1.00 v o = 0.6 [v] r8+r9 r9 v o r8 r9 fb internal reference voltage: 0.6 v fig.24 fig.25 rt vs. switching frequency fig.26 ss capacitance vs. delay time
11/16 (6) phase compensation phase compensation setting procedure the phase compensation setting procedure varies with the selection of capacitance used for dc/dc converter application. in this connection, the following section describes the procedure by classifying into the two types. furthermore, the application stability conditions are described in the ?description? section. 1. application stability conditions 2. for output capacitors having high esr, such as electrolytic capacitor 3. for output capacitors having low esr, such as ceramic capacitor or os-con about application stability conditions the following section shows the stability conditions of negative feedback system. at a 1 (0-db) gain, the phase delay is 150 ? or less (i.e., the phase margin is 30 ? or more). furthermore, since the dc/dc converter application is sampled according to the switching frequency, gbw of the overall system should be set to 1/10 or less of the switching frequency. the following section summarizes the targeted characteristics of this application. at a 1 (0-db) gain, the phase delay is 150 ? or less (i.e., the phase margin is 30 ? or more). the gbw (i.e., frequency at 0-db gain) for this occasion is 1/10 or less of the switching frequency. consequently, in order to upgrade the responsiveness, higher switching frequency should be provided. a knack for ensuring the stability through the phase compensation is to cancel a secondary phase delay (-180 ?) resulting from lc resonance with a secondary phase lead (i.e., through inserting two phase leads). furthermore, the gbw (i.e., frequency at 0-db gain) is determined according to phase compensation capacitance to be provided for the error amplifier. consequently, in order to reduce the gbw, increase the capacitor capacitance. a c r feed back fb point (a) fa= 1.25 [hz] ?` (a) a 0 0 - 90 - 180 1 2prca point (b) fa= gbw [hz] gbw(b) gain [db] phase [deg] - 180? - 90? - 20db/decade 1 2prc (1) typical (sun) integrator (low pass filter) since the error amplifier is provided with (1) or (2) phase compensation, the low pass filter is applied. in the case of the dc/dc converter application, the r becomes a parallel resistance of the feedback resistance. (2) open loop characteristics of integrator fig.27 fig.28
12/16 for output capacitors having high esr, such as aluminum electrolytic capacitor for output capacitors having high esr (i.e., several ohms), the phase compensation setting procedure becomes comparatively simple. since the dc/dc converter application has surely a lc resonant circuit attached to the output, a -180? phase-delay occurs in that area. if esr component is present there, however, a +90 ? phase-lead occurs to shift the phase delay to -90 ?. since the phase delay is desired to set within 150 ? , this is a very effective method but has a demerit to increase the ripple component of the output voltage. according to changes in phase characteristics due to the esr, only one phase lead should be inserted. for this phase lead, select either of the methods shows below. for the purpose of canceling the lc resonance, the frequency to insert the phase lead should be set close to the lc resonant frequency. for output capacitors having low esr, such as ceramic capacitor or os-con unlike the section above, in order to use capacitors having low esr (i.e., several tens of mw), two phase-leads should be inserted so that a -180 phase-delay due to lc resonance will be observed. example (7) blow shows a typical phase compensation procedure. for the settings of phase lead frequency, insert both of the phase leads close to the lc resonant frequency. (4) with esr provided (3) lc resonant circuit (6) insert the r3 in integrator. (5) insert feedback resistance in the c. a fb r3 r2 c2 r1 v o phase lead: f z = [hz] 1 2pc2r3 a fb r2 c2 c1 r1 v o phase lead: f z = [hz] 1 2pc1r1 fig.30 fig.29 fig.32 fig.31 (7) phase compensation with secondary phase lead phase lead: f z1 = [hz] 1 2pr1c1 phase lead: f z2 = [hz] 1 2pr3c2 lc resonant frequency: fr= [hz] 1 2p lc a fb r3 c2 r2 c1 r1 v o fig.33 fr= [hz] at this resonance point, a -180 ? phase-delay occurs. 1 2p lc c l v o v cc fr= [hz]: resonance point a -90? phase-delay occurs. 1 2p lc f esr = [hz]: phase lead 1 2pr esr c c r esr l v o v cc
13/16 equivalent circuit fig.34 equivalent circuit vreg 170 4.rt vreg vcc 20 5k 5k 2.comp1 11.comp2 10 sw 17.boot2 22.boot1 pvcc 14.sw2l 25.sw1l pvcc boot 15.sw2 16.sw2 23.sw1 24.sw1 vcc 100k 2k 50 6.ss1/sdwn 8.ss2/sdwn vreg 2.5k 1k 3.fb1 10.fb2
14/16 1) absolute maximum ratings even though thorough attention is exerted to the quality control of this ic, exceeding the absolute maximum ratings, such as applied voltage, operating temperature range, etc., can break down the ic. should the ic break down, it will be impossible to identify breaking mode such as short circuit mode or an open mode. if any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including use of fuses, etc. 2) gnd potential gndmake setting of the potential of the gnd terminal so that it will be maintained at the minimum in any operating state. 3) thermal design with consideration given to power dissipation (pd) in the actual use state, provide the thermal design with an adequate margin. 4) short circuit between pins and erroneous mounting in order to mount ics on a set printed circuit board, pay thorough attention to the direction and offset of the ics. erroneous mounting can break down the ics. furthermore, if a short circuit occurs due to foreign matters entering between pins or between the pin and the power supply or the gnd pin, the ics can break down. 5) operation in strong electromagnetic field be noted that using ics in the strong electromagnetic field can malfunction them. 6) inspection with set printed circuit board on the inspection with the set printed circuit board, if a capacitor is connected to a low-impedance pin, the ic can suffer stress. therefore, be sure to discharge from the set printed circuit board by each process. for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage of the set printed circuit board. furthermore, in order to connect the jig for the inspection process, be sure to turn off the power supply and then mount the set printed circuit board to the jig. after the completion of the inspection, be sure to turn off the power supply and then dismount the set printed circuit board from the jig. 7) ic pin input this ic is a monolithic ic, which has p+ isolation and p layer between elements to isolate the elements. p-n junction is formed with this p layer and the n layer of each element, thus composing a variety of parasitic elements. for example, as shown in fig. 35, if the resistor and the transistor is connected with the pin respectively, when gnd>(pin a) for the resistor or gnd>(pin b) for the transistor (npn), p-n junction will operate as a parasitic diode. for the transistor (npn), when gnd>(pin b), the parasitic npn transistor will operate with the n layer of other element in the proximity of the said parasitic diode. in terms of the construction of ic, parasitic elements are inevitably formed in relation to potential. the operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the ic. therefore, pay thorough attention not to handle the input pins such as to apply to the input pins a voltage lower than the gnd (p layer) so that any parasitic element will operate. cautions on use gnd p layer n p nn p + p + (pin a) parasitic element resistor (pin a) gnd parasitic element p + p + n transistor (npn) b n p n (pin b) c n p layer gnd parasitic element e gnd b (pin b) parasitic element gnd c e fig.35 typical simple construction of monolithic ic
15/16 power dissipation 1500 0 255075 ambient temperature : ta [?c] power dissipation : pd [mw] 100 125 150 1250 1000 750 500 250 0 fig.37 thermal derating characteristics 8) ground wiring pattern if small-signal gnd and large-current gnd are provided, it will be recommended to separate the large-current gnd pattern from the small-signal gnd pattern and establish a single ground at the reference point of the set pcb so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal gnd. pay attention not to cause fluctuations in the gnd wiring pattern of external parts as well. 9) on the application shown on the right, if the vcc and each output voltage are inverted, for example, if the vcc is short-circuited to the ground with external diode charged, internal circuits or elements may be damaged. to avoid that, use the output pin capacitor in the range of 10 to 100 f. furthermore, in order to use a capacitor of 100 f or more, it is recommended to insert a backflow prevention diode or a bypass diode between the output and vcc. 10) overcurrent protection circuit output has a built-in overcurrent protection circuit according to the current capability, which prevents the destruction of the ic at short-circuiting of load. however, this protection circuit is only effective to prevent destruction due to a sudden accident but does not support for the continuous operation of the protection circuit or use in transition. furthermore, since the current capability has characteristic negative to temperature, give consideration to the thermal design. 11) temperature protection circuit this ic has a built-in temperature protection circuit to prevent the thermal destruction of the ic. as described above, be sure to use this ic within the power dissipation range. should a condition exceeding the power dissipation range continues, the chip temperature tj will rise to activate the temperature protection circuit, thus turning off the output power element. then, when the tip temperature tj falls, the circuit will be automatically reset. furthermore, since the temperature protection circuit is activated under the condition exceeding the absolute maximum ratings, never attempt to use the temperature protection circuit for set design or else. 12) input capacitor in order to derate a peak noise, which occurs while in switching operation, be sure to insert a capacitor (ceramic capacitor) having a low esr of 10 to 100 f as close to the pin as possible between the vcc and ground. fig.36 typical bypass diode application vcc output pin backflow prevention diode bypass diode
package specifications selection of order type b d 9 3 0 2 f p - e 2 product name package/forming specifications 13.6 0.2 25 1 1.9 0.1 0.36 0.1 2.75 0.1 7.8 0.3 13 0.11 0.1 14 5.4 0.2 1.95 0.1 0.8 0.25 0.1 0.3 min. (unit : mm) * please place an order for this ic in multiplies of the quantity per package. package style q?ty per package packaging direction embossed carrier tape 2000 pcs e2 (when holding a reel by left hand and pulling out the tape by right hand, no. 1 pin appears in the upper left of the reel.) hsop25 pulling-out side no. 1 pin reel catalog no. 08t907a '08.12 rohm? the contents described herein are correct as of december, 2008
appendix1-rev3.0 thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact your nearest sales office. rohm customer support system the americas / europe / asia / japan contact us : webmaster@ rohm.co. jp www.rohm.com copyright ? 2008 rohm co.,ltd. 21 saiin mizosaki- cho, ukyo-ku, kyoto 615-8585, japan tel : +81-75-311-2121 fax : +81-75-315-0172 appendix notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of rohm co.,ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing rohm's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from rohm upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, rohm shall bear no respon- sibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. rohm does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by rohm and other parties. rohm shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products are not designed to be radiation tolerant. while rohm always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possi bility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. rohm shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which re quires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). rohm shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the f oreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law.

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